The present invention relates to a three-value data storing semiconductor memory system which comprises a plurality of three-value data storing semiconductor memory devices and a circuit for controlling these semiconductor memory devices.
A so-called "three-value data storing semiconductor memory" is known which has memory cells, each capable of assuming three different data-storing states, and which can therefore have a high integration density. A nonvolatile semiconductor memory which stores three-value data is known. This semiconductor memory comprises a semiconductor substrate and MOS transistors. Each MOS transistor has a floating gate (a charge-storing section) and a control gate, both provided, one on the other, on the semiconductor substrate. Three different amounts of charge are accumulated, one at a time, in the charge-storing section of each memory cell. Each memory can therefore store a three-value data item.
Each memory cell of a three-value data storing semiconductor memory stores a three-value data item, for example, "0,""1" or "2." Hence, two memory cells are used to represent nine different data-storing states. Of these nine states, eight states defines data corresponding to a 3-bit binary data item. In other words, two memory cells cooperate to store a 3-bit data item in the three-value data storing semiconductor memory.
A 3-bit binary data item is converted to two 2-bit binary data items. Each 2-bit binary data item is a three-value data item, which is written into one memory cell by means of a data-writing circuit. The data-writing circuit operates under the control of the 2-bit binary data item. The three-value data item stored in each memory cell is converted into a 2-bit binary data item by a data-reading circuit. Two 2-bit binary data items read from two memory cells are converted into a 3-bit binary data.
Various semiconductor devices, such as CPUs, flash memories and DRAMs, have a data input/output interface for receiving and supplying 2.sup.m binary data items (m=1, 2, 3, . . . ), e.g., eight binary data items or 16 binary data items, at the same time. If the 2.sup.m binary data items are processed to provide 3-bit binary data items, there will remain 1-bit and/or 2-bit binary data items.
For example, if 8-bit binary data is processed to provide 3-bit binary data items, there will be obtained two 3-bit data items and one 2-bit data item. In this case, one bit may be added to the 2-bit data item, thereby forming a pseudo 3-bit data item. Thus, only six memory cells are required to store the 8-bit binary data. This means that the three-value data storing memory needs to have only three quarters (3/4) the number of memory cells which a binary data storing memory have, in order to store the same amount of data. Hereinafter, the value of 3/4 will be referred to as "data compression ratio."
If 2.sup.m, i.e., the number of binary data items used, is a multiple of 3, there will remain neither 1-bit binary data item nor 2-bit binary data items. However, the semiconductor memory needs to a circuit for converting 2.sup.m binary data items, where 2.sup.m is a multiple of 3, into three-value data items, and also a circuit for converting three-value data items into the 2.sup.m binary data items, where 2.sup.m is a multiple of 3. If necessarily provided with these circuits, the semiconductor memory will have its chip size inevitably increased.
In most types of semiconductor memories used at present, data-correction is effected if the data stored has been destroyed. If the data is stored in a three-value data storing memory, all bits of a 3-bit binary data item would become erroneous in the worst case. In some cases, this error may occur in two of the 3-bit binary data items which are output concurrently.
As indicated above, the conventional three-value data storing semiconductor memory in and from which 2.sup.m binary data items are concurrently input and output has but a insufficient data compression ratio or needs to have complex circuits to attain a sufficient data compression ratio.